Leading VLSI Test Experts
23+ years of experience in SOC DFT architecture, pre-silicon implementation, and more
About Us
We are VLSI Test experts with 23 plus years of experience in the cutting-edge SOC DFT architecture, pre-silicon implementation, post-silicon debug, volume production ramp up, yield improvement, and test time optimization. Excellent command on Logic BIST, Scan architecture, ATPG, Memory BIST, JTAG Boundary scan, IJTAG implementation and IEEE 1149.10 standard.
